Current supplies are used in a wide variety of analog circuits. As the term is used herein, a “current supply” can be either a current source that drives current from a higher voltage (e.g., Vcc) through an output load to a lower voltage (e.g., ground), or a current sink that receives current from a higher voltage (e.g., Vcc) through an output load and provides it to a lower voltage (e.g., ground). A current supply should ideally have the following characteristics: (1) maintains a constant current regardless of the voltage level at the output node; and (2) maintains a very high output impedance at all frequencies from DC to infinite frequency.
One very common arrangement used in a current supply is a current mirror arrangement. The objective of the current mirror arrangement is to accurately copy a reference current while attempting to preserve the output characteristics of an ideal current supply, as set forth above.
FIG. 1 illustrates a first embodiment of a current supply 100 having a current mirror arrangement. Current supply 100 is a current mirror arrangement, including a current mirror input stage 120 and a current mirror output stage 160. Current mirror input stage 120 comprises a first transistor 130 that is connected to a constant current source 140 providing a substantially constant current, Iref. Current mirror output stage 160 comprises a second transistor 170 sinking an output current Iload from an output load 190. Because current mirror output stage 160 includes only a single transistor 170, it is sometimes referred to as a “single stack” current mirror arrangement.
In current supply 100, first and second transistors 130 and 170 each have a first terminal, a second terminal, and a control terminal. The first terminal of second transistor 170 is connected to the first terminal of first transistor 130. In the embodiment of FIG. 1, both of these first terminals are connected to ground. In another embodiment the first terminals could be connected to a low supply voltage, including a negative supply voltage. Also, the control terminals of first and second transistors 130 and 170 are connected together to each other. Meanwhile, the second terminal and the control terminal of first transistor 130 are also connected together.
Although current supply 100 is configured as a current sink or “active load,” in another embodiment, the first terminals of first and second transistors 130 and 170 may be connected to a high (e.g., positive Vcc) supply voltage, in which case current supply 100 operates as a current source.
Ideally, the current mirror output stage 160 has two characteristics: (1) its current (Iload) accurately mirrors the current (Iref) through the current mirror input stage 120; and (2) it maintains a very high output impedance from DC to infinite frequency. Equation (1) expresses the relationship between Iload and Iref in the current supply 100:Iload/Iref=[(W2/L2)/(W1/L1)]*[(1+λ*VDS2)/(1+λ*VDS1)]  (1)where: W2 is the channel width of second transistor 170; L2 is the channel length of second transistor 170; W1 is the channel width of first transistor 130; L1 is the channel length of first transistor 130; λ is a process parameter for the fabrication of first and second transistors 130, 170; VDS2 is the drain-to-source voltage of second transistor 170, and VDS1 is the drain-to-source voltage of first transistor 130.
To maintain a current mirror relationship (i.e., Iload=Iref), then first and second transistors 130 and 170 should be perfectly matched. In other words, the ratio W2/L2, for second transistor 170 should be equal to W1/L1 for first transistor 130. In that case, since VGS1=VGS2 in the configuration of FIG. 1, then VDS1≈VDS2. Accordingly, from equation (1), Iload≈Iref.
So the current mirror arrangement of current supply 100 can allow second transistor 170 to maintain a substantially constant output current Iload that substantially mirrors the constant current Iref, despite variations in the impedance of output load 190.
However, there are some disadvantages and limitations to current supply 100. In particular, the output impedance of the second transistor 170 is often not as high as desired. In that case, changes of VDS2 due to changes or perturbations to output load 190 (e.g., ripple or switching noise on a power supply voltage to which output load 190 is connected) can affect the current Iload.
According, to increase the output impedance of the current supply, a current supply having a cascode current mirror arrangement has been developed. Indeed, a number of different cascode current mirror arrangements have been developed.
FIG. 2 shows a current supply 200 having a low-dropout voltage cascode current mirror arrangement. Current supply 200 comprises a biasing circuit 210, a current mirror input stage 220, and a current mirror output stage 260. This arrangement is referred to as “low-dropout voltage” because the voltage across current mirror output stage 260 can drop to a lower voltage level than in a “regular” cascode current mirror arrangement. This arrangement is instead sometimes referred to as a “high-swing” cascode current mirror arrangement because it enables larger voltage swings on the output load.
Current mirror input stage 220 comprises a first transistor 230 and a third transistor 275 that are connected in series with a constant current source 240 providing a current Iref. Current mirror output stage 260 comprises a second transistor 270 and a fourth transistor 280 that are connected in series with an output load 290. Meanwhile, biasing circuit 210 includes a fifth (bias) transistor 295 supporting a current Ibias at a first terminal thereof
In current supply 200, first, second, third, fourth, and fifth transistors 230, 270, 275, 280 and 295 each have a first terminal, a second terminal, and a control terminal. The first terminal of first transistor 230, second transistor 270, and fifth transistor 295 are connected together. In the embodiment of FIG. 2, all of these first terminals are connected to ground. In another embodiment the first terminals of first, second, and fifth transistors 230, 270 and 295 could be connected to a low supply voltage, including a negative supply voltage. Also, the control terminals of first and second transistors 230 and 270 are connected together to each other, and to the second terminal of third transistor 275. Furthermore, the first terminal of third transistor 275 is connected to the second terminal of first transistor 230, and the first terminal of fourth transistor 280 is connected to the second terminal of second transistor 270. Finally, the control terminals of third and fourth transistor 275 and 280 are connected together and are both also connected to the control terminal of fifth transistor 215.
Although current supply 200 is configured as a current sink or “active load,” in another embodiment the first terminals of first, second, and fifth transistors 230, 270, and 295 may be connected to a high (e.g., positive Vcc) supply voltage, in which case current supply 200 operates as a current source.
As explained above, ideally current mirror output stage 260 has two characteristics: (1) its current (Iload) accurately mirrors the current (Iref) through the current mirror input stage 220; and (2) it maintains a very high output impedance from DC to infinite frequency.
In the current supply 200, first, second, third, and fourth transistors 230, 270, 275 and 280 are all operated in saturation. Equation (2) provides that the output current of a current mirror whose output transistor is in saturation is:Iload=K(VGS−VTH)2*(1+λ*VDS)   (2)where K and λ are process parameters.
The current Iref can be perfectly mirrored to Iload if VDS1=VDS2. Meanwhile, in the cascode current mirror arrangement of FIG. 2, VDS1 will equal VDS2 if VGS3=VGS4. Thus fourth transistor 280 effectively shields VDS2 of second transistor 270 from changes or perturbations to output load 290 (e.g., ripple on a power supply voltage to which output load 290 is connected). From FIG. 2 it can be seen that:VDS2=VGS5−VGS3,4  (3)
So the current mirror arrangement of current supply 200 can allow second transistor 270 to maintain a substantially constant output current Iload that substantially mirrors the constant current Iref, despite wide variations in the voltage of output load 290.
However, there are some disadvantages and limitations to current supply 200. In particular, in comparison to the current supply 100, the headroom is substantially reduced. That is, for current supply 100 to remain in saturation, the minimum output voltage VOUT100, is found by Equation (4):VOUT100=VDSSAT2  (4)
In contrast, for current supply 200, the minimum output voltage VOUT200, is found by Equation (5):VOUT200=2*VDSSAT3,4  (5)
In order to reduce VOUT200 to be near to VOUT100, then the size of second and fourth transistors must be substantially increased (quadrupled). That is, the transistors 230, 270, 275, and 280 in current supply 200 must each be four times as large as the transistors 130 and 170 in current supply 100. However, when the size of second and fourth transistors 270 and 280 is increased, then the parasitic capacitance of the devices is also increased. Since impedance is inversely proportional to capacitance at a particular frequency, this means that the output impedance is reduced. This in turn degrades the high frequency performance of the current supply. Meanwhile, as fabrication process parameters continue to shrink, supply voltages of devices are being reduced, and operating frequencies are increasing. As a result, the headroom that is required to maintain the current mirror in saturation limits the maximum output swing of the current supply.
So it is seen that while current supply 200 can improve (increase) the output impedance over current supply 100 at lower frequencies, current supply 200 has a disadvantage that at higher frequencies, its output impedance is decreased compared to current supply 100, given the same headroom.
What is needed, therefore, is a current supply with a high output impedance from DC to a very high frequency that can operate with a low headroom.